Monday, 18. November 2024 until Sunday, 24. November 2024.

  • 2024-11-21T11:30:00+01:00
  • 2024-11-21T14:00:00+01:00
  • Sala Polivalente A0.03. Planta 0. Edificio "A" de la EEBE del Campus Diagonal-Besòs
November

21

Thursday

Nov 21, 2024 from 11:30 AM to 02:00 PM

Títol: Design and Implementation of High-Level Multilevel Inverters: Focusing on 15-level, 25-level, and 33-level Topologies with Asymmetrical Configuration and Optimal Component Choices Direcció : MARTINEZ GARCIA, HERMINIO Codirector: VELASCO QUESADA, GUILLERMO