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Seminari: On-chip Power distribution networks in flip-chip and wire bonded ICs

05/05/2014 de 12:00 a 14:00
Aula-seminari del DEE a l'ETSEIB, planta 9. Diagonal 647
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On-chip Power distribution networks in flip-chip and wire bonded ICs
  • Part I: IR-Drop in on-chip PDNs with non-uniform power consumption

By Prof. Josep Rius

To ensure a good supply voltage throughout a digital IC, the on-chip power distribution network (PDN) is usually organized as a grid of parallel wires in the two or more upper metal layers covering the IC surface. Connection to the package is currently made by two approaches: the so-called peripheral bonding, in which the supply pads are distributed along the sides of the IC, and array bonding, where the supply pads are distributed in an array over the whole IC surface, in a flip-chip package.
The PDN behaves as a conductive mesh with resistive, inductive and capacitive properties. As a consequence, the electric current spikes produced during circuit activity are transformed into voltage bounces at the supply terminals of internal circuits. This power supply noise (PSN) has several undesirable effects on the performance and reliability of ICs. A good PDN design is therefore necessary to reduce the PSN below a specified value. The PSN can be roughly divided into static and dynamic. Static PSN, or IR-drop, is the voltage drop caused by the supply current in the PDN resistances, whereas dynamic PSN is due to transients exciting the PDN inductances and capacitances. The analysis of the IR-drop is important because it allows addressing the most important issues in PDN design, i.e. width and pitch of PDN wires and size, number and location of supply pads. When a dynamic analysis of the PSN is required, there are additional important issues to solve, such as the impact of on-chip PDN inductance and the amount and distribution of on-chip decoupling capacitance.
The design of a good, reliable on-chip PDN of a digital IC is a very complex task because designers cannot anticipate all the details of the design. The PSN depends on the location, size and activity of the circuit blocks. Therefore, in order to check that the PSN is below the specified value, it is necessary to simulate the complete circuit, which is clearly unfeasible for large ICs. The help of specific CAD tools alleviates this problem. However, due to the simulation time, CAD tools are primarily intended for use in post-layout verification, after the design is complete. A failure in the design involves costly rework of the PDN. This leads to over-dimensioning, resulting in the sacrifice of valuable routing resources. For this reason, the use of pre-layout tools in the early stages of PDN design, which give approximate results for the PSN expected, becomes a necessity. In addition, such approximate analytical approaches have the advantage that shows the relationships between the significant PDN parameters, improving the understanding of the problem and allowing their optimization.