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Enrique Barajas Ojeda

Ph.D. Thesis title:
A low-power impulse radio ultra-wideband transceiver for short-range, high-speed wireless communication


Enrique Barajas Ojeda



Dr. Diego Mateo Peña/ José Luis González

Reading day:

29th August 2011 

This research thesis aims to develop a wireless transceiver that combines low power consumption with high data-rates by exploiting short-range communication peculiarities.

The various Ultra-Wideband (UWB) alternatives were studied   low-power Impulse Radio or high-performance OFDM and Direct Sequence   considering the low power consumption and high data-rate requirements, as well as the short-range necessities. Once the system modulation was decided   Impulse Radio UWB  , the analysis at system level was performed in order to determine the optimal system architecture by choosing between the better-performance coherent architecture and the simpler-implementation non-coherent architecture. Furthermore, the analysis of the power consumption of Software Defined Radio (SDR) receivers and transmitters indicated that for extreme low power operation, an analog implementation of the transceiver should be chosen.

These system level simulations were performed with a signal processing simulator (Ptolemy). This has ultimately allowed us to include the non-idealities of the system  noise, interferences and non-linear effects   but also to model the required blocks from the specifications level up to the transistor level. Eventually, the results obtained from these simulations determined that a LNA-less coherent quadrature analog correlator (QAC) architecture was the optimal for this field of operation, and that was the architecture used in the second fabricated prototype.

Additional investigation to reduce the overall power consumption of the system was also done. A behavioral modeling (Verilog-A and Matlab) of the time base generator (TBG) was implemented to reduce simulation times. Moreover, new architectures for this power-hungry block have been proposed in the framework of this thesis. These new architectures exploit a hierarchical organization of the TBG that, if optimally sized and organized, may lead to a minimum energy and power consumption.

The optimization of the performance and power consumption at the circuit level of the different blocks of the RF front-end was also carried out using RF simulators (spectreRF and Agilent-ADS). Novel techniques to optimize the power consumption of the LNA for IR-UWB were proposed and implemented in the first fabricated prototype. Simultaneously, the template generator and mixer topologies were modified to produce a novel merged architecture   designed specifically for IR-UWB   that achieves lower power consumption and better performance that the existing solutions found in literature. This new circuit has been used in the second fabricated prototype.

Along the thesis work the various ideas proposed have been experimentally validated. A first prototype of an IR transceiver was implemented including low-power versions of the LNA and mixer, and a first version of the template generator and some of the blocks used in the TBG (such as the voltage controlled delay line). A second prototype was designed and fabricated that contained the whole RF front-end and part of the base-band blocks. Both circuits were manufactured using a 0.18 um CMOS technology, and measurements of its performance under different case scenarios were made. The last prototype provides state-of-the art energy-per-bit consumption compared with other existing circuits found in the literature.