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Hector Eduardo Aldrete Vidrio

Strategies for built-in characterization testing and performance monitoring of analog RF circuits with temperature measurements

Ph.D. Thesis title:

Strategies for built-in characterization testing and performance monitoring of analog RF circuits with temperature measurements


Hector Eduardo Aldrete Vidrio


Josep Altet Sanahujes

Reading Date:



The trend towards integrating more system functionality on a single chip, including high-performance RF and analogue circuits, requires high-performance measuring instrumentation, which drastically increases the test cost. In addition, the observability of system’s critical nodes and signal paths is further limited, resulting in longer test, debugging time, and significantly longer time to market.
Having electrical access to internal nodes during the debugging phase is of a great support to check the functionality of each block individually and to evaluate the effects of process, voltage and temperature variations on system’s performance. The traditional characterization approach requires extra I/O nodes and, in the case of RF nodes, on-chip impedance matching networks altogether with RF buffers are also needed. Usually, after a de-embedding process, the circuit under test (CUT) is characterized using an external RF test bench including network and spectrum analyzers.
The International Technology Roadmap for Semiconductors suggests the use of built-in test (BiT) circuits as a solution to increase the observability of analogue and RF systems. Main requirements for on-chip monitoring circuitry include small area and power overhead and preferable non-invasive signal detection to eliminate undesirable loading effects on the CUT.
What this thesis proposes is a novel BiT strategy for analogue and RF circuits aimed to increase system’s observability without neither additional RF I/O pads nor high-cost RF measurement equipment. In this BiT approach, the monitoring circuitry is located near enough to the device and signal paths, but it is not physically connected to the system under characterization. Thus, the tested nodes are not loaded, avoiding the system performance degradation.
The figures of merits of the analogue and RF circuits are observed by measuring the temperature at the silicon surface with the aid of efficient temperature sensors placed close to the CUT. Measuring temperature to determine electrical figures of merits is an attractive solution as the CUT is non-invasive solution. The temperature monitoring system detects the information from the intrinsic thermal coupling provided by the silicon substrate. It has been shown during this research work that the electrical performance of the CUT can be observed using CMOS embedded tiny temperature sensors. The temperature sensor used requires 0.0042 mm2 active silicon area in a 0.25 μm technology and has 117 mV/mW sensitivity (at 25 μm away from the CUT). This type of sensor allows observing the
frequency-gain characteristic of narrow-band amplifiers.
The proposed strategies allow the performance mentoring of RF devices using low-frequency spectral measurements. The characterization method is based on power measurement using two-tone RF signature with frequencies close to each other. Since power is proportional to v2, the generated low-frequency power components at the frequency difference of the test tones allow CUT performance monitoring at low frequencies. The temperature sensor topology can be used for different RF circuits working at different spectral bands, unifying and simplifying the required measuring equipment.
As a step on the way to achieving a system level BiT approach, the most effort of the experimentation in this work is focused on the characterization testing and performance monitoring of 1 GHz LNA: frequency-gain response, center frequency and linearity (1-dB compression point).