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SUMMARY:PhD Thesis Defense: Francisco Javier Galindo Guarch
DTSTART;TZID=Europe/Madrid:20210701T100000
DTEND;TZID=Europe/Madrid:20210701T110000
DTSTAMP:20260505T021333Z
UID:b081731d4e204d3ea0b3caae3c89baad@electronicengineering.phd.upc.edu
CREATED:20210520T063208Z
DESCRIPTION:Títol: HARDWARE ARCHITECTURES FOR BEAM SYNCHRONOUS PROCESSING
  AND RF SYNCHRONIZATION OF PARTICLE ACCELERATORS\nDirectors: Juan Manuel M
 oreno Arostegui\nCodirector: Philippe BAUDRENGHIEN
LAST-MODIFIED:20210520T063315Z
LOCATION:https://meet.google.com/bgn-doaz-cxt (Videoconferència)
URL:https://electronicengineering.phd.upc.edu/en/events/phd-thesis-defense
 -francisco-javier-galindo-guarch
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TZID:Europe/Madrid
X-LIC-LOCATION:Europe/Madrid
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DTSTART:20210328T030000
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
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