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SUMMARY:PhD Thesis Defense: Bernardo Javier Vallejo Mancero
DTSTART;TZID=Europe/Madrid:20241111T110000
DTEND;TZID=Europe/Madrid:20241111T140000
DTSTAMP:20260623T073746Z
UID:d32543ba24344292959ede454f785e12@electronicengineering.phd.upc.edu
CREATED:20241022T071454Z
DESCRIPTION:Title: Highly scalable hardware architecture for real-time exe
 cution of spiking neural networks applied to neural cognitive applications
 \nThesis director:  MADRENAS BOADAS\, JORDI/ ZAPATA RODRÍGUEZ\, MIREYA PA
 TRICIA
LAST-MODIFIED:20241022T071503Z
LOCATION:Aula de Graus (C4002)\, campus nord
URL:https://electronicengineering.phd.upc.edu/en/events/phd-thesis-defense
 -bernardo-javier-vallejo-mancero
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TZID:Europe/Madrid
X-LIC-LOCATION:Europe/Madrid
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DTSTART:20241027T020000
TZNAME:CET
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
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